aircraft digital electronic and computer systems pdf free download

aircraft digital electronic and computer systems pdf free download

Aaj Tak. Hamilton movie Lists with This Book. This book is not yet featured on Listopia. Community Reviews. Showing Average rating 4. Rating details. All Languages. More filters. Sort order. Vetree rated it it was amazing Dec 23, Saimon rated it it was amazing Aug 30, Vishal Gupta rated it it was amazing Jun 05, Emmanmicu rated it it was ok Oct 08, Omar Seyadi rated it it was amazing Mar 18, Asit Kumar rated it really liked it Apr 28, Chan Wai rated it it was amazing Oct 25, Lyon Bolivar rated it liked it Feb 06, Retrieved April 21, Consider the car.

A modern car contains many separate computer systems for controlling such things as the engine timing, the brakes, and the airbags. Clemson University. Retrieved September 20, University of Arkansas. Archived from the original on October 12, Carnegie Mellon University.

Retrieved December 5, The Silicon Engine. Computer History Museum. Retrieved October 9, History of Semiconductor Engineering. Johns Hopkins University Press. Proceedings of the IEEE. Those of us active in silicon material and device research during — considered this successful effort by the Bell Labs group led by Atalla to stabilize the silicon surface the most important and significant technology advance, which blazed the trail that led to silicon integrated circuit technology developments in the second phase and volume production in the third phase.

World Scientific. December 4, Retrieved July 20, August 6, Retrieved July 21, Retrieved July 22, Case School of Engineering. Retrieved November 29, The two main logic families are further divided into a number of different sub-families based on variations in the parent technology. Which of the devices shown is a two-input OR gate? What voltage would you expect to measure on pin 14 of a device?

Sketch a circuit including pin numbers showing how a device could be used as a dual R-S bistable. Sketch circuits including pin numbers showing how a could be used as: a a two-input AND gate; and b a two-input OR gate. The most appropriate logic family for use in a portable item of test equipment is: 1. The logic device shown in Figure 5. The logic gate arrangement shown in Figure 5.

The normal supply voltage for a TTL logic device is: a 2. A two-input NAND gate will produce a logic 0 output when: 8. The noise margin for standard TTL devices is: a both of the inputs are at logic 0 a mV b either one of the inputs is at logic 0 b mV c both of the inputs are at logic 1.

In a binary counter, the clock input of each 9. If a voltage of 3 V is measured at the input to the gate, this would be considered equivalent to: a the same clock line b the Q output of the previous stage a logic 0 c the CLEAR line.

The device shown in Figure 5. The truth table shown in Figure 5. This chip hardware and software and are capable of processing is equivalent to many thousands of individual tran- large amounts of data in a very short time.

This sistors. The clock usually consists of a high- trol signals throughout the system. The number of individual lines present within the address bus and data bus depends upon the particular microprocessor employed.

Signals on all lines, no 6. Data and addresses are repre- — particularly large ones — are not very convenient. This format Some basic microprocessors designed for control is easier for mere humans to comprehend and also and instrumentation applications have an 8-bit offers the significant advantage over base 10 numbers data bus and a bit address bus.

More sophisticated in that numbers can be converted to and from binary processors can operate with as many as 64 or bits with ease. A group of eight bits, operated on as a unit, is The largest binary number that can appear on an referred to as a byte. Since hexadecimal characters can 8-bit data bus corresponds to the condition when all be represented by a group of four bits, a byte of data eight lines are at logic 1.

Therefore the largest value can be expressed using two hexadecimal characters. Similarly, the highest address that can appear value ranging from 00 to FF. The basic unit of data that on a bit address bus is or can be manipulated as an entity is often referred to 65, The full range of data values and addresses as a word.

Words can be any convenient length, but for a simple microprocessor of this type is thus: , and bit words are common see Table 6. Data from A single byte of data can be stored at each address to within the total memory space of a computer system. Hence, one byte can be stored at each of the 65, Addresses from memory locations within a microprocessor system to having a bit address bus.

Individual bits within a byte are numbered from 0 least significant bit, or Finally, a locally generated clock signal provides a time LSB to 7 most significant bit, MSB. In the case of reference for synchronising the transfer of data within bit words which are stored in consecutive mem- ory locations the bits are numbered from 0 LSB to 15 MSB. Table 6. For example, the signed 8-bit number by a memory device we usually use Kilobytes Kbyte. It is important to note that a Kilobyte of memory is actually 1, bytes not 1, bytes.

The capacity of a semiconductor ROM is usually 1. What is the highest data value expressed specified in terms of an address range and the num- in decimal that can appear on a bit ber of bits stored at each address.

What is the decimal equivalent of the 4 Kbytes , and so on. Note that it is not always nec- signed 8-bit binary number ? This is important since our programs often involve moving sizeable blocks of data into and out of memory. The basic element of a semiconductor memory 6.

Cells can be fabricated in one of two semiconductor technologies: MOS metal oxide The semiconductor ROM within a microprocessor semiconductor and bipolar. Bipolar memories are system provides storage for the program code, as well now rarely used even though they offer much faster as any permanent data that requires storage. All of this access times. Their disadvantage is associated with data is referred to as non-volatile because it remains power supply requirements they need several voltage intact when the power supply is disconnected.

Part of the RAM dynamic types. The important difference between the is also used by the microprocessor as a temporary two types is that dynamic memories require periodic store for data while carrying out its normal processing refreshing if they are not to lose their contents.

While, tasks. This function has to be integrated with that, as for the bipolar cell, the SET and RESET lines the normal operation of the computer system, or are common to a number of cells.

Static memories do not need refreshing and is shown in Figure 6. In contrast to the previous can be relied upon to retain their memory until such types of cell this clearly does not use a bistable time as new data is written or the power supply is arrangement. Instead, a capacitor, C, is used as the interrupted in which case all data is lost. The capacitor is in fact the input The circuit of a typical bipolar static memory capacitance of an MOS transistor.

This is charged or cell is shown in Figure 6. The character- by means of a pulse applied to the appropriate istics of a number of common RAMs are shown in emitter. This type of cell uses examples have been included.

Note that there is some emitter-coupled logic ECL and requires both nega- variation in the way these memories are organised.

From Table 6. This is also clearly recognisable decoding in order to make each cell individually as a bistable element. This is achieved by arranging the cells in to gate signals into and out of the memory cell.

Note the form of a matrix. Figure 6. Each cell within the array has a unique address and is selected by plac- ing appropriate logic signals on the row and column address lines. All that is necessary to interface the memory matrix to the system is some additional logic, but first we must consider the mechanism which allows the address bus to be connected to the memory cell. The row and column decoders of Figure 6. Each possible combination of the seven input lines results in the selection of a unique output line.

If we assume that the row decoder handles the most significant part 6. This is achieved by multiplexing to memory location 0 memory address h , part of the address bus and then de-multiplexing it whereas the corresponding position in the next row within the memory device.

A typical arrangement is will be memory address h. Finally, the cell shown in Figure 6. The multiplexing inelegant since, with the aid of some additional gating arrangement for the address bus is shown in Figure and latches, it is possible to reduce the number of 6. This table present within the system.

Such a precaution is essen- assumes that the most significant part of the address tial in order to prevent data conflicts in which more high order appears first and is decoded to the than one memory cell in different RAM blocks is appropriate row while the least significant low order addressed simultaneously.

Cell no. For a complete byte eight bits we would One-time programmable electrically programmable ROM obviously require eight such devices. The memory cells bus. Various methods are employed for data transfer consist of nichrome or polysilicon fuse links between into and out of the matrix, sensing the state of either rows and columns.

Data output is generally tri- and programming can be carried out by the computer state see page 60 by virtue of the shared data bus. This facility is, of course, necessary for the long-term semi-permanent storage of oper- ating systems and high-level language interpreters. To change the control program or constant data it is necessary to replace the ROM. This is a simple matter because ROMs are usually plug-in devices or can be programmed electrically.

The following types are in common use. Mask-programmed ROM. This relatively expensive process is suitable for very high volume production several thousand units or more and involves the use of a mask that programs links within the ROM chip. Unlike the two circumstances such a system can be relied upon to previous types of ROM, the EPROM can be re- retain stored information for a year or more. The EPROM may be individual cells within the matrix are uniquely refer- erased by exposure to a strong ultraviolet light source enced by means of row and column address lines.

ROMs vary in capacity and 64K, K and K Once erasure has taken place any previously applied devices are commonplace. The programming Finally, it is important to note that ROM and process is carried out by the manufacturer from mas- EPROM devices do not lose their data when the supply ter software using a dedicated programming device is disconnected.

They are thus said to be non-volatile which supplies pulses to establish the state of indi- memories NVM. Most RAM devices, unless battery- vidual memory cells. This process usually takes several backed see page 72 , are volatile memories and the minutes though some EPROM programmers can stored data will be lost when the supply is disconnected.

This type of ROM can both be read to and written from. Clearly a more meaningful program impacts on the characteristics, performance representation is required! Computer memories are either more understandable at least for humans is to write volatile or non-volatile the latter preserving the program in a number base with which we are its contents when the power supply is familiar. For this purpose we could choose octal base disconnected. The non-volatile, while most types of RAM are decimal equivalent of the above program code would, volatile, unless battery-backed.

We would, A program is simply a sequence of instructions that of course, still require some means of converting tells the computer to perform a particular operation. A better instruction comprises a unique pattern of binary method, and one which we introduced you to in digits. It should, however, be noted that the computer Chapter 2, uses hexadecimal. This code into its equivalent hexadecimal by arranging the information must also be presented to the micro- binary values into groups of four bits and then con- processor in the form of binary bit patterns.

Clearly verting each four-bit group at a time. For example, it is necessary for the processor to distinguish between taking the first byte of the program that we met the instruction itself and any data or memory address earlier: which may accompany it. Furthermore, instructions must be carried out in strict sequence.

A computer program may exist in one of several Similarly: forms, although ultimately the only form usable by the processor is that which is presented in binary. The presented in binary is for an Intel x86 family or simple addition program that we met earlier in its Pentium processor: binary form takes on the following appearance when written in hex: B8, 01, 00, BB, 02, 00, 01, D8, 89, C1, F4 While it still does not make much sense unless you just happen to be familiar with x86 machine language programming!

Furthermore, the conversion to and from binary has been a relatively simple matter. An instruction set is the name given to the complete For the load instruction to be meaningful we need range of instructions that can be used with any partic- to tell the processor which register is to be loaded and ular microprocessor.

It should be noted that although with what. This information, which is known as an there are many similarities, instruction sets are unique operand, must also be contained in the instruction.

In some Thus, if we wished to load the bit accumulator reg- cases manufacturers have attempted to ensure that ister known as the AX register of an Intel processor their own product range of microprocessors share a with a bit data value equivalent to 01 hexadecimal, common sub-set of instructions. This permits the use we would use the instruction: of common software, simplifies development and helps make improvements in microprocessors more MOV AX,01h acceptable to equipment designers and manufac- turers.

These proces- specified the address in hexadecimal. If, alternatively, sors share a common sub-set of instructions and thus we simply wished to copy the contents of the AX a program written for the now obsolete register into the CX register we would write: processor will run on a Pentium-based system. Sophisticated microprocessors offer a large num- MOV CX,AX ber of instructions; so much so, in fact, that the sheer number and variety of instructions can often be Notice how the destination register appears before the bewildering.

It is also rather too easy to confuse the source register. Each of these two instructions has its power of a microprocessor with the number of own hexadecimal representation, the first being: instructions that are available from its instruction set; these two things are not always directly related.

B8, 01, 00 Instructions are presented to the microprocessor in words that occupy one or more complete bytes and the second: often one, two, three or four bytes depending upon the processor and whether it is an 8-bit or , or 89, C1 bit type.

These instruction words are sent to a register within the processor that is known appro- Notice how the first instruction consists of three priately as the Instruction Register. A program written in instruction code mnemonics 6. The process of converting the mnemonics to their hexa- Most people find instructions written in hex rather decimal equivalents is known as assembly and, while difficult to remember, even though one does get to it is possible to translate assembly language programs know some of the more common hex codes after to hexadecimal by referring to instruction code tables working with a particular processor over a period of i.

What is needed, therefore, is a simple method what tedious and repetitious task and one which is of remembering instructions in a form that is mean- very much prone to error. Instead, we use a computer ingful to the programmer. To this end, microprocessor program to perform this task. This assembler program manufacturers provide us with mnemonics for their accepts source code written in assembly language instruction codes.

They are given in a shorthand form and converts this to object code that the CPU can that has some minor variations from one manufacturer execute.

One of the most common instructions is The simple addition program that we met on page associated with loading or moving data into a register. Comments can be useful for maintenance or OUT Output byte or word to a specified port subsequent debugging. Logical instructions Table 6. Note also that the OR Logical OR of byte or word individual registers see Chapter 7 may be either gen- eral purpose or may have some specific purpose such XOR Logical exclusive-OR of byte or word as acting as an accumulator or as a counter.

Such a system may incorporate several PUSHF Push flags onto stack microprocessors each of which has its own support devices and local bus system or may involve just a POPF Pop flags off stack single microprocessor again with support devices and ESC Escape to external processor interface its own local bus operating in conjunction with a number of less intelligent supporting cards. A high degree of modularity also allows cards to be exchanged when faults HLT Halt processor develop, or interchanged between systems for testing.

The user is thus able to minimise down-time and need not be concerned with board-level servicing as cards Finally, as a further example of the use of assembly can be returned to manufacturers or their appointed language mnemonics, the following short code frag- and suitably equipped service agents.

Systems that can do this are referred to as LOOP getdata and go around again multiprocessing systems. Note that while several bus RET return to main program. In systems that support more than one potential bus master, a system of bus arbitration must be employed to eliminate possible contentions for con- trol of the bus.

Several techniques are used to establish bus priority and these generally fall into two classes, serial and parallel. In a serially arbitrated system, bus access is granted according to a priority that is based on the physical slot location. Each master present on the bus notifies the next lower-priority master when it needs to gain access to the bus.

It also monitors the bus request status of the next higher-priority master. The masters thus pass bus requests on from one to the next in a 6. Various sub-architectures, including the use of a local Both systems have their advantages and disadvantages mezzanine bus, are possible within the overall VME and some bus standards permit the use of both tech- framework.

Further standards apply to these systems. The standard resulted from a joint effort between 2. Explain what is meant by the following semiconductor manufacturers Mostek, Motorola and terms: a backplane bus; b bus master; c Signetics to establish a framework for 8-, and bus slave.

Explain the need for bus arbitration in a supporting both single and multiple processors. The multi-processor system. Describe two methods of bus arbitration. The basic 5. Give an example of a commonly used back- VME standard defines four main buses present within plane bus standard. The data transfer bus, which provides a means of transferring data between bus cards. The priority interrupt bus, which provides a 6.

To help put this chapter into context, we shall con- 3. The arbitration bus, which provides a means of clude with a brief overview of two simple computer determining which processor or bus master has systems found in large transport aircraft. The infor- control of the bus at any particular time. The utility bus, which provides a means of approaches to computer architecture and the inter- distributing power and also synchronising power- connections made with other aircraft avionic systems. The master timing signal for the clock current time.

This makes them ideal candidates for the is derived from an accurate crystal oscillator. The QAR is able to search for and replay data from a specified GMT reference before subsequently systems in which multiple processors have returning to the current recording position. The feature marked Q in Figure 6. Some of these systems are based on the use of a single 2. In Figure 6. The processor instruction HLT is classed as: a a control instruction b a data transfer instruction c a logical instruction.

What type of memory uses the principle of b R charge storage: c S. The memory cell shown in Figure 6. What is the largest hexadecimal address that can c a bipolar static cell. Bus arbitration is required in order to: a prevent memory loss b avoid bus contention c reduce errors caused by noise and EMI. A memory device in which any item of data can 6.

A memory device has a pin marked CAS. The A bus arbitration system based on the physical function of this pin is: location of cards is referred to as: a chip active select a serial arbitration b control address signal b parallel arbitration c column address select.

A semiconductor memory consists of rows and columns. The capacity of this memory will be: a bits b bits c 64K bits. The primary function of the microprocessor is that of fetching, 7. As such, it must be able to transfer data from The accumulator functions both as a source and as a external memory into its own internal registers and destination register for many of the basic micro- vice versa. Furthermore, it must operate predictably, processor operations.

In addi- result of a particular operation. The accumulator or tion, various system housekeeping tasks need to be A register features in a very large number of micro- performed, including being able to suspend normal processor operations, consequently more reference is processing in order to respond to an external device made to this register than any other.

Program 1. The instruction is 3. Each machine cycle takes a finite time usually within the system. Figure 7. In an 8-bit system, together. Data is constantly flowing backwards and the data bus has eight data lines, labelled D0 the least forwards along the internal data bus lines.

With a bit data bus the data lines are labelled D0 7. Many microprocessor operations for example, adding two 8-bit numbers together require the use of more 7. There is also a requirement for temporarily storing the partial result of an operation The data bus buffer is a temporary register through while other operations take place. Both of these needs which bytes of data pass on their way into and out of can be met by providing a number of general purpose the microprocessor.

The buffer is thus referred to as registers. The editors will have a look at it as soon as possible. Delete template? Cancel Delete. Cancel Overwrite Save. Don't wait!

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