advanced computer architecture kai hwang third edition pdf free download

advanced computer architecture kai hwang third edition pdf free download

Linda Null. Updated and revised, The Essentials of Computer Organization and Architecture, Third Edition is a comprehensive resource that addresses all of the necessary organization and architecture topics, yet is appropriate for the one-term course. Nikrouz Faroughi. Similar ebooks. Kai Hwang. The definitive guide to successfully integrating social, mobile, Big-Data analytics, cloud and IoT principles and technologies The main goal of this book is to spur the development of effective big-data computing operations on smart clouds that are fully supported by IoT sensing, machine learning and analytics systems.

The first book describing a practical approach to integrating social, mobile, analytics, cloud and IoT SMACT principles and technologies Covers theory and computing techniques and technologies, making it suitable for use in both computer science and electrical engineering programs Offers an extremely well-informed vision of future intelligent and cognitive computing environments integrating SMACT technologies Fully illustrated throughout with examples, figures and approximately problems to support and reinforce learning Features a companion website with an instructor manual and PowerPoint slides www.

John L. Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices.

The book, which became a part of Intel's recommended reading list for developers, covers the revolution of mobile computing. It also highlights the two most important factors in architecture today: parallelism and memory hierarchy. Part of Intel's Recommended Reading List for DevelopersUpdated to cover the mobile computing revolutionEmphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.

Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends "What's Next" Includes three review appendices in the printed text.

Includes updated Case Studies and completely new exercises. Distributed and Cloud Computing: From Parallel Processing to the Internet of Things offers complete coverage of modern distributed computing technology including clusters, the grid, service-oriented architecture, massively parallel processors, peer-to-peer networking, and cloud computing. It is the first modern, up-to-date distributed systems textbook; it explains how to create high-performance, scalable, reliable systems, exposing the design principles, architecture, and innovative applications of parallel, distributed, and cloud computing systems.

Scientific Storytelling A science-writing initiative will empower Kenyon students to artfully articulate important scientific topics. The Significance of String Professor of Anthropology Bruce Hardy makes headlines for his study on the cognitive abilities of Neanderthals.

Jul 17 Kenyon in Your Kitchen pm — pm Kenyon alumni working in food and drink industries are sharing their go-to happy hour pairings. Just need a basic editor to be able… Jul 24 Kenyon in Your Kitchen pm — pm Kenyon alumni working in food and drink industries are sharing their go-to happy hour pairings. In general, the execution of a program may involve a combination of these levels.

The actual combination depends on the application, formulation, algorithm, language, program, compilation support, and hardware limitations. We characterize below the parallelism levels and review their implementation issues from the viewpoints of a pro- grammer and of a compiler writer.

Instruction Level At instruction or statement level. Depending on individual programs, fine- grain parallelism at this level may range from two to thousands. Butler et al. Wall finds that the average parallelism at instruction level is around five, rarely exceeding seven, in an ordinary program.

For scientific applications, Kumar has measured the av- erage parallelism in the range of to Fortran statements executing concurrently in an idealized environment. The advantage of fine-grain computation lies in the abundance of parallelism. The exploitation of fine-grain parallelism can be assisted by an optimizing compiler which should be able to automatically detect parallelism and translate the source code to a parallel form which can be recognized by the run-time system.

Instruction-level paral- lelism is rather tedious for an ordinary programmer to detect in a source code. Loop Level This corresponds to the iterative loop operations. A typical loop contains less than instructions. Some loop operations, if independent ; n successive iterations, can be vectorized for pipelined execution or for lock-step execution on SIMD machines. Reprinted from Hwang, Proc. Loop-level parallelism is the most optimized program construct to execute on a parallel or vector computer.

However, recursive loops are rather difficult to parallelize. Vector processing is mostly exploited at the loop level level 2 in Fig. The loop level is still considered a fine grain of computation. P r o c e d u r e Level This level corresponds to medium-grain size at the task, procedu- ral, subroutine, and coroutine levels.

A typical grain at this level contains less than instructions. Detection of parallelism at this level is much more difficult than at the finer-grain levels. Interprocedural dependence analysis is much more involved and history-sensitive. The communication requirement is often less compared with that required in MIMD execution mode.

SPMD execution mode is a special case at this level. Multitasking also belongs in this category. Significant efforts by programmers may be needed to restructure a program at this level, and some compiler assistance is also needed.

S u b p r o g r a m Level This corresponds to the level of job steps and related subpro- grams. The grain size may typically contain thousands of instructions,.

Subprograms can be scheduled for different processors in Limited preview! Multiprogramming on a uniprocessor or on a multiprocessor is conducted at this level. In the past, parallelism at this level has been exploited by algorithm designers or programmers, rather than by compilers.

We do not have good compilers for exploiting medium- or coarse-grain parallelism at present. Job Program Level This corresponds to the parallel execution of essentially in- dependent jobs programs on a parallel computer. The grain size can be as high as tens of thousands of instructions in a single program.

For supercomputers with a small number of very powerful processors, such coarse-grain parallelism is practical. Job-level parallelism is handled by the program loader and by the operating system in general.

Time-sharing or space-sharing multiprocessors explore this level of parallelism. In fact, both time and space sharing are extensions of multiprogramming. To summarize, fine-grain parallelism is often exploited at instruction or loop levels, preferably assisted by a parallelizing or vectorizing compiler. Medium-grain parallelism at the task or job step demands significant roles for the programmer as well as compilers.

Coarse-grain parallelism at the program level relies heavily on an effective OS and on the efficiency of the algorithm used. Shared-variable communication is often used to support fine-grain and medium-grain computations. Mess age-passing multicomputers have been used for medium- and coarse-grain com- putations. In general, the finer the grain size, the higher the potential for parallelism and the higher the communication and scheduling overhead. Fine grain provides a higher degree of parallelism, but heavier communication overhead, as compared with coarse-grain computations.

Communication Latency By balancing granularity and latency, one can achieve better performance of a computer system. Various latencies are attributed to machine architecture, implementing technology, and communication patterns involved.

The ar- chitecture and technology affect the design choices for latency tolerance between sub- systems. In fact, latency imposes a limiting factor on the scalability of the machine size. For example, memory latency increases with respect to memory capacity. Thus mem- ory cannot be increased indefinitely without exceeding the tolerance level of the access latency. Various latency hiding or tolerating techniques will be studied in Chapter 9.

The latency incurred with interprocessor communication is another important pa- rameter for a system designer to minimize. Besider; signal delays in the data path, IPC latency is also affected by the communication patterns involved. Thus the complexity grows quadratically. This leads to a communication bound which limits the number of processors allowed in a large computer system.

Communication patterns are determined by the algorithms used as well as by the architectural support provided. Frequently encountered patterns include permutations and broadcast, multicast, and conference many-to-many communications. The com- munication demand may limit the granularity or parallelism. Very often tradeoffs do exist between the two. We will study techniques that minimize communication latency, prevent deadlock, and optimize grain size throughout the hook. This grain-size problem demands determination of both the number and the size of grains or microtasks in a parallel program.

Of course, the solution is both problem- dependent and machine-dependent. The goal is to produce a short schedule for fast execution of subdivided program modules. The time complexity involves both computation and communication overheads The program partitioning involves the algorithm designer, programmer, compiler, op- erating system support, etc. We describe below a grain packing approach introduced by Kruatrachue and Lewis for parallel programming applications. In Fig.

A program graph shows the structure of a program. It is very similar to the dependence graph introduced in Section 2. Each node in the program graph corresponds to a computational unit in the program. The grain size is measured by the number of basic machine cycles including both processor and memory cycles needed to execute all the operations within the node.

We denote each node in Fig. G by a pair n, s , where n is the node name id and s is the grain size of the node. Thus grain size reflects the number of computations involved in a program segment.

Fine-grain nodes have a smaller grain size, and coarse-grain nodes have a larger grain size. The edge label v, d between two end nodes specifies the output variable v from the source node or the input variable to the destination node, and the communi- cation delay d between them. This delay includes all the path delays and memory latency involved. There are 17 nodes in the fine-grain program graph Fig.

The coarse-grain node is obtained by combining grouping multiple fine-grain nodes. Each takes one cycle to address and six cycles to fetch from memory. All remaining nodes 7 to 17 are CPU operations, each requiring two cycles to complete. After packing, the coarse-grain nodes have larger grain sizes ranging from 4 to 8 as shown. The node A,8 in Fig. Then one combines packs multiple fine-grain nodes into a coarse- grain node if it can eliminate unnecessary communications delays or reduce the overall scheduling overhead.

Usually, all fine-grain operations within a single coarse-grain node are assigned to the same processor for execution. Fine-grain partition of a program often demands more interprocessor communication than that required in a coarse-grain partition.

Internal delays among fine-grain operations within the same coarse-grain node are negligible because the communication delay is contributed mainly by interprocessor delays rather than by delays within the same processor.

The choice of the optimal grain size is meant to achieve the shortest schedule for the nodes on a parallel computer system. I: idle time; shaded areas: communication delays With respect to the fine-grain versus coarse-grain program graphs in Fig.

The fine-grain schedule is longer 42 time units because more communication delays were included as shown by the shaded area. The coarse-grain schedule is shorter 38 time units because communication delays among nodes 12, 13, and 14 within the same node D and also the delays among 15, 16, and 17 within the node E are eliminated after grain packing.

In general, dynamic multiprocessor scheduling is an NP-hard problem. Very often heuristics are used to yield suboptimal solutions. We introduce below the basic concepts behind multiprocessor scheduling using static schemes.

Node Duplication In order to eliminate the idle time and to further reduce the communication delays among processors, one can duplicate some of the nodes in more than one processor. Figure 2. This schedule contains idle time as well as long interprocessor delays 8 units between P I and P2.

The new schedule shown in Fig. The reduction in schedule time is caused by elimination of the a, 8 and c, 8 delays between the two processors. I: idle time; shaded areas: communication delays Grain packing and node duplication are often used jointly to determine the best grain size and corresponding schedule. Four major steps are involved in the grain determination and the process of scheduling optimization: Step 1.

Construct a fine-grain program graph. Step 2. Schedule the fine-grain computation. Step 3. Grain packing to produce the coarse grains- Step 4. Generate a parallel schedule based on the packed graph. The purpose of multiprocessor scheduling is to obtain a minimal time schedule for the computations involved.

The following example clarifies this concept. In this example, two 2 x 2 matrices A and B are multiplied to compute the sum of the four elements in the resulting product matrix C — A x B. Note that the communication delays have slowed down the parallel execution signifi- cantly, resulting in many processors idling indicated by I , except for P i which produces the final sum. Next we show how to use grain packing Step 3 to reduce the communication overhead.

The remaining three nodes N, O, P then form the fifth node Z. Note that there is only one level of interprocessor communication required as marked by d in Fig. Since the maximum degree of parallelism is now reduced to 4 in the program graph, we use only four processors to execute this coarse-grain program. Dataflow computers are based on a data-driven mechanism which allows the execution of anv instruction to be driven by data operand availability.

Dataflow computers emphasize a high degree of parallelism at the fine-grain instructional level. Reduction computers are based on a demand-driven mechanism which initiates an operation based oa the demand for its results by other computations.

The data-driven chain reactions are shown in Fig. Note that no shared memory is used in the dataflow implemen- tation. The example does not show any time advantage of dataflow execution over control flow execution. The chain reaction control in dataflow is more difficult to implement and may result in longer overhead, as compared with the uniform operations performed by all the processors in Fig. Thus, instruction-level parallelism of dataflow graphs can absorb the communication latency and minimize the losses due to synchronization waits.

Besides token matching and I-structure, compiler technology is also needed to generate dataflow graphs for tagged-token dataflow computers. The dataflow architecture offers an ideal model for massively parallel computations because all far-reaching side effects are removed. Side effects refer to the modification of some shared variables by unrelated operations.

Such a computation has been called eager eval- uation because operations are carried out immediately after all their operands become available. A demand-driven computation corresponds to lazy evaluation, because operations are executed only when their results are required by another instruction.

The demand- driven approach matches naturally with the functional programming concept. The removal of side effects in functional programming makes programs easier to parallelize.

There are two types of reduction machine models, both having a recursive control mech- anism as characterized below.

Reduction Machine Models In a string reduction model, each demander gets a separate copy of the expression for its own evaluation. A long string expression is Limited preview! These routing functions can be implemented on ring, mesh, hypercube, or multistage networks. The set of all permutations form a permutation group with respect to a composition operation. One can use cycle notation to specify a permutation function.

The cycle a,b,c has a period of 3, and the cycle d, e a period of 2. One can use a crossbar switch to implement the permutation. Multistage networks can implement some of the permutations in one or multiple passes through the network.

Permutations can also be implemented with shifting or broadcast operations. The permutation capability of a network is often used to indicate the data routing capability. When n is large, the permutation speed often dominates the performance of a data- routing network. Perfect Shuffle and Exchange Perfect shuffle is a special permutation function suggested by Harold Stone for parallel processing applications.

The mapping corresponding to a perfect shuffle is shown in Fig. Its inverse is shown on the right-hand side Fig. It is symmetric with a constant node degree of 2. The IBM token ring has this topology, in which messages circulate along the ring until they reach the destination with a matching token.

Pipelined or packet-switched, rings have been implemented in the CDC Cyberplus multiprocessor and in the KSR-1 computer system for interprocessor communications.

By increasing the node degree from 2 to 3 or 4, we obtain two chordal rings as shown in Figs. One and two extra links are added to produce the two chordal rings, respectively. In general, the more links added, the higher the node degree and the shorter the network diameter. Comparing the node ring Fig. In the extreme, the completely connected network in Fig. Barrel Shifter As shown in Fig. Obviously, the connectivity in the barrel shifter is increased over that of any chordal ring of lower node degree.

But the barrel shifter complexity is still much lower than that of the completely connected network Fig. Tree and S t a r A binary tree of 31 nodes in five levels is shown in Fig.

The maximum node degree is 3 and the diameter is 2 fc - 1. With a constant node degree, the binary tree is a scalable architecture. However, the diameter is rather long. Note that the pure mesh as shown in Fig. The node degrees at the boundary and corner nodes are 3 or 2. The Illiac IV assumed an 8 x 8 Illiac mesh with a constant node degree of 4 and a diameter of 7. The Illiac mesh is topologically equivalent to a chordal ring of degree 4 as shown in Fig.

The torus shown in Fig. This topology combines the ring and mesh and extends to higher dimensions. The torus has ring connections along each row and along each column of the array. The torus is a symmetric topology. All added wraparound connections help reduce the diameter by one-half from that of the mesh. Systolic Arrays This is a class of multidimensional pipelined array architectures designed for implementing fixed algorithms.

What is shown in Fig. The interior node degree is 6 in this example. In general, static systolic arrays are pipelined with multidirectional flow of data streams. The commercial machine Intel iWarp system Anaratone et al. The systolic array has become a popular research area ever since its introduction by Kung and Leiserson in With fixed interconnection and synchronous operation, a systolic array matches the communication structure of the algorithm.

However, the structure has limited applicability and can be very difficult to program. Since this book emphasizes general-purpose computing, we will not study systolic arrays further. Interested readers may refer to the book by S. Kung for using systolic and wavefront architectures in building VLSI array processors. A 3-cube with 8 nodes is shown in Fig. A 4-cube can be formed by interconnecting the corresponding nodes of two 3- cubes, as illustrated in Fig.

The node degree of an n-cube equals n and so does the network diameter. In fact, the node degree increases linearly with respect to the dimension, making it difficult to consider the hypercube a scalable architecture. Binary hypercube has been a very popular architecture for research and devel- opment in the s. The architecture has dense connections. Many other architectures, such as binary trees, meshes, etc.

With poor scalability and difficulty in packaging higher-dimensional hypercubes, the hypercube architecture is gradually being replaced by other architectures. For Limited preview! But the CCC has a node degree of 3, smaller than the node degree of 6 in a 6-cube. In this sense, the CCC is a better architecture for building scalable systems if latency can be tolerated in some way. The parameter n is the dimension of the cube and k is the radix, or the number of nodes multiplicity along each dimension.

For sim- plicity, all links are assumed bidirectional. Each line in the network represents two communication channels, one in each direction. Traditionally, low-dimensional fc-ary n-cubes are called torit and high-dimensional binary n-cubes are called hypercubes- The long end-around connections in a torus can be avoided by folding the network as shown in Fig.

In this case, all links along the ring in each dimension have equal wire length when the multidimensional network Limited preview! Other boards for processors, memories, or device interfaces are plugged into the backplane board via connectors or cables.

The passive or slave devices memories or peripherals respond to the requests. The common bus is used on a time-sharing basis, and important busing issues include the bus arbitration, interrupts handling, coherence protocols, and transaction processing.

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